The present invention relates generally to MOS devices incorporated in integrated circuits and in particular the present invention relates to an integrated circuit having a MOS capacitor.
Integrated circuits incorporate complex electrical components formed in semiconductor material into a single device. Generally, an integrated circuit comprises a substrate upon which a variety of circuit components are formed wherein each of the circuit components are electrically isolated from each other. Integrated circuits are made of semiconductor material. Semiconductor material is material that has a resistance that lies between that of a conductor and an insulator. Semiconductor material is used to make electrical devices that exploit its resistive properties. A common type of semiconductor structure is the metal-oxide semiconductor (MOS).
Semiconductor material is typically doped to be either a N type or a P type. N type semiconductor material is doped with a donor type impurity that generally conducts current via electrons. P type semiconductor material is doped with an acceptor-type impurity that conducts current mainly via hole migration. A N type or P type having a high impurity or high dopant concentration or density is denoted by a xe2x80x9c+xe2x80x9d sign. A N type or P type having a low impurity or low dopant concentration or density is denoted by a xe2x80x9cxe2x88x92xe2x80x9d sign.
A capacitor can be formed using a MOS structure. A capacitor is a device that holds an electrical charge. A capacitor comprises a dielectric positioned between a top plate and a bottom plate. Typically, a capacitor of an integrated circuit is formed using the semiconductor material of a substrate as the bottom plate. An integrated circuit may comprise a plurality of capacitors created from a single substrate to form a circuit. Generally, MOS capacitors consume a relatively significant amount of area in many analog circuits.
A typical MOS capacitor formed in an integrated circuit comprises a heavily doped semiconductor surface as a bottom plate, a silicon dioxide (oxide) as a dielectric layer and a metal interconnect or poly layer as a top plate. The capacitance of this type of capacitor is given by the equation C=xcex5A/T, where C=capacitance, xcex5=the dielectric constant of material that makes up the dielectric, A=the area of the capacitor plate and T=thickness of the dielectric. One method of reducing the capacitor area in an integrated circuit is by substituting silicon nitride (nitride) for the oxide as the dielectric. The dielectric constant of nitride is approximately 7/3.9 that of oxide. In addition, the two films, nitride and oxide, have about the same voltage blocking strength (rupture electric fields) so a layer of the same thickness can be used. Accordingly, the substitution of a layer nitride in place of a layer of oxide of the same thickness will reduce the capacitor area by about 44%.
Typically, the nitride is deposited over the entire substrate surface by low pressure chemical vapor deposition (LPCVD) or plasma enhance chemical vapor deposition (PECVD). The nitride is then patterned to form contact apertures or contact openings. This process usually, involves an extra pattering step when nitride overlays oxide that is not required when the oxide layer is used. Extra pattering steps add cost to the manufacture of integrated circuits. It is desired in the art to form an integrated circuit with reduced process steps.
For the reasons stated above and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for forming an integrated circuit having a MOS capacitor with reduced process steps.
The above-mentioned problems are addressed, as well as other problems, by the present invention and will be understood by reading and studying the following specification.
In one embodiment, a method of forming a contact opening through a dielectric layer overlaying an oxide layer in an integrated circuit is disclosed. The method comprises forming a layer of mask material overlaying the dielectric layer. Patterning the layer of mask material to expose a pre-selected portion of the nitride layer and forming anisotropic contact openings that extend through the layer of dielectric and the layer of oxide using a dry etch with a single mask.
In another embodiment, a method of forming an integrated circuit is disclosed. The method comprises forming an oxide layer on a surface of a substrate, the substrate having a plurality of isolation islands, wherein at least one isolated island is used in forming a semiconductor device. Patterning the oxide layer to expose predetermined areas of the surface of the substrate. Depositing a nitride layer overlaying the oxide layer and the exposed surface areas of the substrate and implanting ions through the nitride layer. The nitride layer is used as an implant screen for the implanted ions.
In another embodiment, a method of forming an integrated circuit. The method comprises. Forming an oxide layer on a surface of a substrate. The substrate has a plurality of isolation islands. At least one isolation island is used to form a semiconductor device of the integrated circuit. Patterning the oxide layer to expose predetermined areas of the surface of the substrate. Depositing a dielectric layer overlaying the oxide layer and the exposed surface areas of the substrate. The dielectric layer has a higher dielectric constant than a dielectric constant of the oxide layer. Implanting ions through the dielectric layer. Diffusing the ions to form device regions in selected isolation islands in the substrate and using the dielectric layer in at least one of the isolation islands as a capacitor dielectric in forming a capacitor.
In another embodiment, a method of forming an integrated circuit is disclosed. The method comprising forming a first oxide layer on a surface of a substrate. The substrate has a plurality of isolation islands. At least one isolation island is used in forming a semiconductor device of the integrated circuit. Patterning the first oxide layer to expose predetermined areas of the surface of the substrate. Implanting and diffusing ions through the second oxide layer into the substrate to form device regions. Forming a dielectric layer overlaying the oxide layer and the exposed areas of the surface of the substrate. The dielectric layer has a dielectric constant higher than a dielectric constant of the oxide layer. Using the dielectric layer in at least one of the isolation islands as a capacitor dielectric in forming a capacitor.
In another embodiment, a method of forming a capacitor and a transistor in an integrated circuit. The method comprising, forming a plurality of isolation islands in a substrate of a first conductivity type with low dopant density. The substrate contains a capacitor isolation island to form the capacitor in and a transistor isolation island to form the transistor in. Forming a base of a second conductivity type in the transistor isolation island adjacent a surface of the substrate. Forming a layer of oxide on a surface of the substrate. Patterning the layer of oxide to form pre-selected exposed surface areas of the substrate. Forming a layer of dielectric over the layer of oxide and the exposed surface areas of the substrate. Implanting dopants of the first conductivity type with high dopant density through the layer of dielectric into the substrate. Diffusing the dopants to form a bottom plate in the capacitor isolation island and an emitter and collector contact in the transistor isolation island. The emitter is formed in a portion of the base. The bottom plate, the emitter and the collector contact are formed adjacent the surface of the substrate. Using a dry etch to form contact opening through the dielectric layer to the bottom plate in the capacitor isolation island. Using a dry etch to form a contact opening through the dielectric layer and the oxide layer to the base in the transistor isolation island. Using a dry etch to form a contact opening through the dielectric layer to the collector contact and the emitter in the transistor isolation island. Forming a layer of metal overlaying the dielectric layer and the contact openings and etching the layer of metal to form a top plate and a bottom plate contact region in the capacitor isolation region and an emitter contact region, a base contact region and a collector contact region in the transistor isolation region.
In another embodiment, an integrated circuit is disclosed. The integrated circuit comprises, a substrate, a layer of oxide, a layer of dielectric and at least one capacitor. The substrate has a plurality of isolation islands. At least one isolation island has a semiconductor device formed therein. The layer of oxide is formed and patterned on a surface of the substrate. The layer of dielectric is formed overlaying the layer of oxide and exposed surface areas of the substrate. The layer of dielectric has a dielectric constant that is higher than the dielectric constant of the layer of oxide. Moreover, the dielectric layer is used as an implant screen in implanting dopants into respective isolation islands to form device regions for the at least one semiconductor device. The at least one capacitor is formed in one of the isolated islands in the substrate. Each capacitor uses the layer of dielectric as a capacitor dielectric. Each capacitor dielectric is positioned between a top plate and a bottom plate.
In another embodiment, an integrated circuit is disclosed. The integrated circuit comprises, a substrate, a layer of oxide, a layer of dielectric and at least one capacitor. The substrate has a plurality of isolation islands. At least one isolation island has a semiconductor device formed therein. The layer of oxide is formed and patterned on a surface of the substrate. The layer of dielectric is formed overlaying the layer of oxide and exposed surface areas of the substrate. The layer of dielectric has a dielectric constant that is higher than the dielectric constant of the layer of oxide. The layer of dielectric and the layer of oxide have anisotropic openings to expose device regions in the substrate. The openings are formed by a dry etch. The at least one capacitor is formed in one of the isolated island in the substrate. Each capacitor uses the layer of dielectric as a capacitor dielectric. Each capacitor dielectric is positioned between a top plate and a bottom plate.
In another embodiment, an integrated circuit is disclosed. The integrated circuit comprises a substrate, one or more semiconductor devices, a oxide layer, a nitride layer and at least one capacitor. The substrate has a surface and a plurality of isolation islands. Each semiconductor device is formed in an associated isolation island. Some of the semiconductor devices have device regions formed adjacent the surface of the substrate. The oxide layer is formed and patterned on the surface of the substrate. The nitride layer overlays the patterned oxide layer and any exposed surface area of the substrate. The oxide and nitride layers that overlay select device regions have a contact opening to the device region that is formed by a dry etch. The at least one capacitor is formed in one of the isolation islands. The at least one capacitor also has a capacitor dielectric that is formed from a portion of the nitride layer.